The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 15, 2026

Filed:

Jun. 12, 2024
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Sangpil Nam, Suwon-si, KR;

Byungwoo Koo, Suwon-si, KR;

Sunghan Do, Suwon-si, KR;

Jungho Lee, Suwon-si, KR;

Youngjae Cho, Suwon-si, KR;

Michael Choi, Suwon-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03M 1/72 (2006.01); H03K 3/84 (2006.01); H03M 1/66 (2006.01);
U.S. Cl.
CPC ...
H03M 1/66 (2013.01); H03K 3/84 (2013.01);
Abstract

A digital-to-analog converter (DAC) circuit is provided. The DAC circuit includes: a serializer circuit including a plurality of multiplexers and configured to convert a parallel code in digital form into a serial code using the plurality of multiplexers; and a cell array including a plurality of unit cells and configured to output an analog signal based on the serial code. The serializer circuit includes: a pseudo random number generation circuit configured to generate random numbers in response to edges of a first clock signal; a first switch circuit connected to a first multiplexer; a second switch circuit connected to a second multiplexer; and a random number circuit configured to transmit different random numbers generated by the pseudo random number generation circuit in response to different edges of the first clock signal to the first switch circuit and the second switch circuit, respectively.


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