High performance data latching using an energy efficient clocked latch topology

Abstract

In an embodiment, a latch device includes a functional clock input node configured to receive a functional clock signal that periodically transitions between an active phase and an inactive phase; and a latch circuit comprising a plurality of gates, the latch circuit configured to latch a data value at an input node based on the functional clock signal being in the active phase; and output the data value at an output node until a different data value is received at the data input node; wherein the plurality of gates includes a plurality of clocked gates and a plurality of non-clocked gates, the plurality of clocked gates including a maximum of three clocked gates; and wherein the latch circuit preserves a static state in the plurality of non-clocked gates across clock transitions as long as the data value at the data input node matches the latched data value.