The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 15, 2026

Filed:

Oct. 21, 2024
Applicant:

SK Hynix Inc., Icheon-si, KR;

Inventors:

Chang Hyun Han, Icheon-si, KR;

Moon Soo Sung, Icheon-si, KR;

Assignee:

SK hynix Inc., Icheon-si, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/10 (2006.01); G11C 16/30 (2006.01); G11C 16/34 (2006.01);
U.S. Cl.
CPC ...
G11C 16/3459 (2013.01); G11C 16/10 (2013.01); G11C 16/30 (2013.01);
Abstract

Provided herein is a memory device and a method of performing a verify operation of the memory device. The memory device includes a memory cell array including memory cells, a source line discharge transistor configured to couple a source line of the memory cell array to a ground, a voltage generator configured to generate a gate voltage that is applied to a gate of the source line discharge transistor, and a control logic configured to determine the gate voltage depending on changes in threshold voltages of the memory cells in response to a verify operation on the memory cells performed in each of a plurality of program loops and to control the voltage generator to generate the determined gate voltage.


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