The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 15, 2026
Filed:
Sep. 26, 2024
Applicant:
Sandisk Technologies, Inc., Milpitas, CA (US);
Inventors:
Mohammad Mahmoodi, Santa Barbara, CA (US);
Zahra Fahimi, Santa Barbara, CA (US);
Martin Lueker-Boden, Fremont, CA (US);
Assignee:
Sandisk Technologies, Inc., Milpitas, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/10 (2006.01); G11C 5/06 (2006.01); G11C 16/24 (2006.01);
U.S. Cl.
CPC ...
G11C 16/102 (2013.01); G11C 5/063 (2013.01); G11C 16/24 (2013.01);
Abstract
An apparatus is provided that includes a memory array including non-volatile memory cells configured to store weights of an artificial neural network, a bit line coupled to a plurality of the non-volatile memory cells, and an interface circuit coupled to the bit line, the interface circuit configured to amplify an output impedance of the memory array.
Mahmoodi, Mohammad. (2026). Apparatus and methods for modifying impedances in time-based vector-matrix multiplication circuits (U.S. Patent No. 12738322). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12738322
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile