The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 15, 2026
Filed:
Jun. 28, 2024
Huawei Technologies Co., Ltd., Shenzhen, CN;
Leibin Ni, Shenzhen, CN;
Zhihang Wu, Boulogne Billancourt, FR;
Wei Wu, Shenzhen, CN;
Song MA, Shenzhen, CN;
Huawei Technologies Co., LTD., Shenzhen, CN;
Abstract
Examples of circuits, multiplier-adders, and circuit optimization methods are described. One example circuit includes a digital addition circuit and an analog addition circuit. The digital addition circuit is configured to perform bitwise digital accumulation on bits that belong to a first bit position range and that are in a plurality of groups of partial products. The plurality of groups of partial products are obtained by multiplying a plurality of first values by a plurality of second values. The first bit position range refers to S bit positions of a product value of one of the first values and one of the second values. S is a positive integer. The product value is obtained by performing bitwise accumulation after a group of partial products are shifted.