Decision feedback equalizer, and memory device and memory system including the same

Abstract

A decision feedback equalizer (DFE) includes an adder including a first node and a second node, and the adder configured to: receive an input signal, amplify a voltage difference between a reference voltage level and a voltage level of the input signal, and output a first internal signal from the first node and a second internal signal from the second node, a first DFE tap configured to provide a first tap bias current to one of the first node and the second node, based on a first sample signal corresponding to an immediately preceding bit of the input signal, and a tap bias voltage generation circuit configured to provide the first DFE tap with a first tap bias voltage corresponding to the first tap bias current, based on the DQ bias voltage, a tap code, and a temperature code depending on a temperature of the DFE.