The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 15, 2026

Filed:

Jun. 01, 2022
Applicant:

Batelab Co., Ltd., Suzhou, CN;

Inventor:

Zhen Li, Suzhou, CN;

Assignee:

BATELAB CO., LTD., Suzhou, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 30/31 (2020.01); G06F 8/20 (2018.01); G06F 8/77 (2018.01); G06F 30/3308 (2020.01); G06F 30/337 (2020.01); G06F 30/367 (2020.01); G06F 30/373 (2020.01); G06F 30/398 (2020.01); G06F 119/02 (2020.01); G06F 119/06 (2020.01); G06F 119/08 (2020.01); G06F 119/18 (2020.01);
U.S. Cl.
CPC ...
G06F 30/31 (2020.01); G06F 8/20 (2013.01); G06F 8/77 (2013.01); G06F 30/373 (2020.01); G06F 30/3308 (2020.01); G06F 30/337 (2020.01); G06F 30/367 (2020.01); G06F 30/398 (2020.01); G06F 2119/02 (2020.01); G06F 2119/06 (2020.01); G06F 2119/08 (2020.01); G06F 2119/18 (2020.01);
Abstract

The present application discloses a chip design method using secondary development capability of EDA software. On the basis of a chip having design and verification of a main function being completed, the feature steps comprise: customizing and adding, on an EDA software development platform, parameters required for an operating environment corresponding to the chip, automatically adding a schematic diagram of at least one of an environmental stabilization system used for implementing temperature compensation and an environmental stabilization system used for implementing electromagnetic shielding, combining same with a chip schematic diagram and drawing to obtain a layout. According to the method, the optimization operation of adding an environmental stabilization system is separated from design of the main function of the chip, and on the basis that design and verification of the main function of the chip are completed and the original chip design layout is kept with few changes, the secondary development capability of EDA software is used for separately optimizing and automatically adding the environmental stabilization system to the original chip design layout; thus, the difficulty and time consumption in chip design are reduced to the greatest extent, and the chip can obtain the capability of normally implementing functions in temperatures and electromagnetic environments that are more severe than those expected in the original design.


Find Patent Forward Citations

Li, Zhen. (2026). Chip design method using secondary development capability of eda software (U.S. Patent No. 12737517). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12737517

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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