Cxl switch with integrated memory channels for accelerated ai workloads

Abstract

Embodiments for communicating using a switch that includes first and second dies. The first die includes first and second sets of Compute Express Link (CXL) upstream switch ports (USPs) and downstream switch ports (DSPs), and routing hardware. The second die includes CXL Root Ports (RPs) coupled to the second set of USPs, CXL Endpoints (EPs) coupled to the second set of DSPs, and DRAM memory channels coupled to DRAM memory modules. A computer monitors data traffic through the USPs and DSPs, stores frequently accessed data in the DRAM memory modules, and utilizes the DRAM memory modules as a cache. Optionally, the DRAM memory modules includes at least 4 GB of memory capacity organized in multiple channels enabling concurrent cache operations.