Programmable, scalable, and performant virtual-to-physical address translation for remote direct memory access (rdma) and other protocols

Abstract

Embodiments herein describe programmable, scalable, and performant virtual-to-physical address translation for remote direct memory access (RDMA) and other protocols. A discrete-logic virtual address-to-physical address (VA2PA) circuit translates addresses based on table lookups. Multiple instances of the VA2PA circuit may be distributed amongst stages of a pipeline to translate addresses for the respective stages, independent of one another. The VA2PA circuit may translate addresses based on multiple translation modes, which may be specified in opcodes of memory access requests. Based on the opcodes, the VA2PA circuit may translate, fetch, and/or probe virtual address translation structures, and may provide translation services specific to remote direct memory access (RDMA) devices. The discrete-logic of the VA2PA circuits provide relatively low latency, while the lookup tables and opcodes provide software-like flexibility/adaptability. The software-like flexibility/adaptability may be useful to support various translations options (e.g., modes/protocols), translation points within a pipeline, and/or to adapt to future protocols/concepts.