Data storage device and method for bit error rate (ber) balancing based on dynamic sense time

Abstract

When data is stored in a multi-level memory, the bit error rate among the various pages in the memory may be unbalanced. Different read-sense timings can be applied to different logical pages to mitigate this problem. More specifically, the sense time used to read a page can be based on a number of read thresholds involved in reading the page. For example, in quad-level cells (QLCs) configured to store top, upper, middle, and lower pages of data, and the sensing times for the top, upper, middle, and lower pages can progressively increase. Dynamically adjusting a voltage stabilization period of a read voltage can significantly reduce read latency and power consumption, which may be desired, for example, when retrieving data at multiple read resolutions or when supporting page-by-page programming.