The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 08, 2026

Filed:

Oct. 09, 2023
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Hyun Soo Chung, Suwon-si, KR;

Young Lyong Kim, Suwon-si, KR;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H10W 90/00 (2026.01); H10B 80/00 (2026.01); H10W 70/685 (2026.01); H10W 72/00 (2026.01); H10W 74/10 (2026.01);
U.S. Cl.
CPC ...
H10W 90/00 (2026.01); H10B 80/00 (2023.02); H10W 70/685 (2026.01); H10W 74/111 (2026.01); H10W 72/823 (2026.01); H10W 90/721 (2026.01); H10W 90/722 (2026.01); H10W 90/724 (2026.01);
Abstract

A semiconductor package may include a circuit board, an interposer structure on the circuit board, a mold layer, and a first semiconductor chip and a second semiconductor chip spaced apart from each other in a first direction on a center region of the interposer structure and electrically connected to the interposer structure. The interposer structure may include a plurality of trenches in an edge region of the interposer structure and extending through the interposer structure. The mold layer may be in the plurality of trenches and may wrap the first and second semiconductor chips. The mold layer may include a penetrating portion in the plurality of trenches and a stack portion on the interposer structure. A bottom surface of the penetrating portion of the mold layer may be on a same plane as a bottom surface of the interposer structure.


Find Patent Forward Citations

Chung, Hyun. (2026). Semiconductor package (U.S. Patent No. 12733555). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12733555

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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