The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 08, 2026

Filed:

Dec. 14, 2021
Applicant:

Rohm Co., Ltd., Kyoto, JP;

Inventors:

Koshun Saito, Kyoto, JP;

Kota Ise, Kyoto, JP;

Kosuke Yamada, Kyoto, JP;

Assignee:

ROHM CO., LTD., Kyoto, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H10W 70/40 (2026.01); H10W 72/00 (2026.01); H10W 72/60 (2026.01); H10W 72/90 (2026.01); H10W 90/00 (2026.01); H10D 12/00 (2025.01); H10D 30/47 (2025.01);
U.S. Cl.
CPC ...
H10W 70/40 (2026.01); H10W 70/415 (2026.01); H10W 70/417 (2026.01); H10W 70/442 (2026.01); H10W 72/60 (2026.01); H10W 72/647 (2026.01); H10W 72/886 (2026.01); H10W 72/932 (2026.01); H10W 90/736 (2026.01); H10W 90/767 (2026.01); H10D 12/411 (2025.01); H10D 30/471 (2025.01); H10W 70/424 (2026.01); H10W 70/427 (2026.01); H10W 70/438 (2026.01); H10W 70/466 (2026.01); H10W 70/481 (2026.01); H10W 72/01361 (2026.01); H10W 72/016 (2026.01); H10W 72/642 (2026.01); H10W 72/871 (2026.01); H10W 72/884 (2026.01); H10W 90/757 (2026.01);
Abstract

A semiconductor device manufacturing method includes a first preparation step, a second preparation step, a mounting step, a third preparation step, a placing step and a curing step. In the first preparation step, a first leadframe including an island part is prepared. In the second preparation step, a semiconductor element including an element obverse surface, an element reverse surface, a first electrode and a second electrode is prepared. In the mounting step, the semiconductor element is mounted on the island part with a first conductive paste interposed between the element reverse surface and the island part. In the third preparation step, a second leadframe including a first part, a second part, a frame part, a first connecting part and a second connecting part is prepared. In the placing step, the second leadframe is placed with a second conductive paste interposed between the first part and the first electrode and with a third conductive paste interposed between the second part and the second electrode. In the curing step, the first conductive paste, the second conductive paste and the third conductive paste are hardened.


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