The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 08, 2026

Filed:

Jan. 17, 2025
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Cheolhwan Lim, Suwon-si, KR;

Kwangho Kim, Yongin-si, KR;

Sangjin Lim, Osan-si, KR;

Haejung Choi, Daegu, KR;

Donghun Heo, Hwaseong-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G01J 1/42 (2006.01); G11C 29/12 (2006.01); H03K 19/003 (2006.01); H10W 42/40 (2026.01);
U.S. Cl.
CPC ...
H10W 42/405 (2026.01); G01J 1/4257 (2013.01); G11C 29/12 (2013.01); H03K 19/00315 (2013.01);
Abstract

A laser detecting circuit is provided. The laser detecting circuit includes a latch circuit with a first inverter configured to invert a first output signal at a first node to generate a second output signal at a second node, and a second inverter configured to generate the first output signal based on the second output signal. The second inverter includes a plurality of PMOS transistors connected in series between a first source voltage and the first node, and a plurality of NMOS transistors. A gate of each of the plurality of PMOS transistors is connected to the second node, and a drain of each of the plurality of NMOS transistors is connected to the first node. The plurality of NMOS transistors includes dummy NMOS transistors and normal NMOS transistors.


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