The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 08, 2026

Filed:

Aug. 19, 2022
Applicant:

Electronics and Telecommunications Research Institute, Daejeon, KR;

Inventors:

Hyun Wook Jung, Daejeon, KR;

Seong Il Kim, Daejeon, KR;

Hae Cheon Kim, Daejeon, KR;

Youn Sub Noh, Daejeon, KR;

Ho Kyun Ahn, Daejeon, KR;

Sang Heung Lee, Daejeon, KR;

Jong Won Lim, Daejeon, KR;

Sung Jae Chang, Daejeon, KR;

Il Gyu Choi, Daejeon, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10D 30/47 (2025.01); H10D 30/01 (2025.01); H10D 64/01 (2025.01); H10D 64/27 (2025.01);
U.S. Cl.
CPC ...
H10D 30/475 (2025.01); H10D 30/015 (2025.01); H10D 64/01 (2025.01); H10D 64/518 (2025.01);
Abstract

Provided are a nitride-based high electron mobility transistor having enhanced frequency characteristics and an improved structural stability and manufacturing method thereof. The nitride-based high electron mobility transistor includes a first semiconductor layer and a second semiconductor layer sequentially formed on a substrate, source drain electrodes formed on the second semiconductor layer, a first insulating film formed on the second semiconductor layer and having an opening, a dielectric formed on the first insulating film to surround the opening of the first insulating film, a second insulating film formed on an inner sidewall of the dielectric, and a gate electrode formed on the dielectric to fill the opening of the first insulating film and inside the inner sidewall of the dielectric. A width of the inner sidewall at a bottom end of the dielectric is smaller than a width of the inner sidewall at a top end of the dielectric.


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