The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 08, 2026

Filed:

Feb. 07, 2024
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Heejae Chae, Suwon-si, KR;

Taejin Park, Suwon-si, KR;

Hyunjin Lee, Suwon-si, KR;

Hosang Lee, Suwon-si, KR;

Yun Choi, Suwon-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10B 12/00 (2023.01); H10D 64/66 (2025.01); H10W 10/00 (2026.01); H10W 10/17 (2026.01);
U.S. Cl.
CPC ...
H10B 12/488 (2023.02); H10D 64/661 (2025.01); H10W 10/0145 (2026.01); H10W 10/17 (2026.01); H10B 12/34 (2023.02);
Abstract

A semiconductor device includes a substrate including a word line trench extending in a first horizontal direction; a gate dielectric layer in the word line trench; a word line extending in the first horizontal direction and in a lower portion of the word line trench on the gate dielectric layer; an insulation capping layer extending in an upper portion of the word line trench on the word line; and a plurality of gate electrodes on the substrate, wherein the word line comprises: a word line lower region extending in the first horizontal direction and including a first gate electrode of the plurality of gate electrodes on the gate dielectric layer; and a word line upper region extending in the first horizontal direction on the word line lower region and including a plurality of second gate electrodes of the plurality of gate electrodes and the first gate electrode.


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