The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 08, 2026

Filed:

Apr. 23, 2024
Applicant:

Nanya Technology Corporation, New Taipei city, TW;

Inventor:

Chia Che Chiang, New Taipei City, TW;

Assignee:

NANYA TECHNOLOGY CORPORATION, New Taipei City, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10B 12/00 (2023.01);
U.S. Cl.
CPC ...
H10B 12/315 (2023.02); H10B 12/033 (2023.02);
Abstract

The present disclosure provides a semiconductor structure and a forming method thereof. The semiconductor structure includes a plurality of bit-line structures laterally spaced apart on a substrate, a landing pad between the bit-line structures, a metal oxynitride layer covered onto the top surface of the landing pad, and a capacitor structure vertically extending above the landing pad. The method of forming a semiconductor structure includes the following operations. A plurality of bit-line structures on a substrate is received. A landing pad is formed between the bit-line structures. A metal oxynitride layer is formed to cover the top surface of the landing pad. A sacrificial stack is formed on top of the metal oxynitride layer and the bit-line structures. A trench is formed in the sacrificial stack to expose the metal oxynitride layer. A capacitor structure is formed in the trench.


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Chiang, Chia. (2026). Semiconductor structure and forming method thereof (U.S. Patent No. 12733149). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12733149

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