High-speed single-ended-to-differential converter with skew control

Abstract

Disclosed is single-ended-to-differential converter circuit implemented in an electrical integrated circuit (EIC) co-packaged with a photonic integrated circuit (PIC) using a system-in-package (SiP) architecture. A reverse-biased photodiode supplies a single-ended signal that is converted to complementary differential outputs. Adjustable skew correctors in the two differential branches are driven by a skew detection circuit that asynchronously samples the differential outputs using a non-synchronized clock. A delay detector with sampler, error detector, and counters estimates branch delay difference from the ratio of accumulated sampling errors to clock cycles, enabling robust skew detection and automatic correction without clock recovery or synchronization. The approach exploits the signal-to-noise ratio (SNR) and common-mode noise rejection of differential signaling while tolerating large data-rate variability, supporting high-speed links such as 56-Gb/s PAM4 used in data centers. The technique improves timing integrity, reduces bit-error rate, and simplifies integration with downstream current-mode logic (CML) stages.