Low-jitter random clock generation circuit

Abstract

A low-jitter random clock generation circuit includes: a clock division and pulse generation module connected to an input clock, performing frequency division processing to obtain frequency division clocks, and then detecting some frequency division clocks one by one to obtain frequency division pulses in a one-to-one correspondence; a pseudorandom number generation module connected to one frequency division clock, and generating a pseudorandom number; a status control module connected to all the frequency division clocks and the pseudorandom number to generate status control signals; and a random clock output module connected to the input clock, all the frequency division clocks, all the frequency division pulses, and all the status control signals, randomly sampling the frequency division clocks by using the frequency division pulses under control of the status control signals, and synchronously outputting the randomly sampled frequency division clocks by using the input clock, to obtain random clocks.