The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 08, 2026
Filed:
Sep. 18, 2024
Applicant:
Xilinx, Inc., San Jose, CA (US);
Inventors:
Tabrez Alam, Hyderabad, IN;
Kumar Rahul, Hyderabad, IN;
Santosh Yachareni, Hyderabad, IN;
Ishtiaque Ahmad, Hyderabad, IN;
Assignee:
XILINX, INC., San Jose, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 3/037 (2006.01); H03K 3/3562 (2006.01); H03K 19/08 (2006.01); H03K 19/094 (2006.01);
U.S. Cl.
CPC ...
H03K 3/0372 (2013.01); H03K 3/35625 (2013.01); H03K 19/0806 (2013.01); H03K 19/09425 (2013.01);
Abstract
Embodiments herein describe single event upset (SEU) tolerant flip-flop that includes master latch circuitry, slave latch circuitry, and a tristate driver having an input coupled to an output of the master latch circuitry and an output coupled to a first data input of the slave latch circuitry, where the first tristate driver is configured to inhibit charge transfer from the first data input of the slave latch circuitry to the output of the master latch circuitry.