Power clamp circuit and electronic device including power clamp circuit

Abstract

A power clamp circuit includes an electro-static discharge (ESD) current discharge circuit including a first MOS transistor, a second MOS transistor, and a third MOS transistor that are coupled in series between a first power rail coupled to a supply voltage and a second power rail coupled to a ground voltage, a first triggering circuit including a first resistor, a first capacitor, and a fourth MOS transistor and configured to trigger the first MOS transistor, a second triggering circuit including a second resistor, a second capacitor, and a fifth MOS transistor and configured to trigger the second MOS transistor, and a third triggering circuit including a third resistor and a third capacitor, and configured to turn off the third MOS transistor during a normal operation and turn on the third MOS transistor when an ESD event occurs.