Efficient training method for unmatched data output path in non-volatile memory

Abstract

To reduce power consumption and circuitry requirements, the following presents an 'unmatched' data output architecture, in which the clock path does not mimic the data path. To provide proper data transfers in the data output path, the clock signal is tuned at points of the clock path, such as for data transfers from internal data buses to FIFOs and from the FIFO though the multiplexers to the input/output pads. An amount of timing offset is introduced in the generation of internal transfer clocks, which can be determined as part of a valid data window training process that can be performed by the controller, such as part of the power up process. To more quickly train the memory dies and determine the timing offset for an unmatched data output architecture, replica circuits for the data path and the clock path can be introduced on to the memory dies.