Lifetime mixed level non-volatile memory system

Abstract

A system for storing data comprises a processor that processes data. At least one MLC non-volatile memory comprises a plurality of individually erasable physical blocks. At least one SLC non-volatile memory comprises a plurality of individually erasable physical blocks. A controller coupled to the at least one MLC non-volatile memory and the at least one SLC non-volatile memory is adapted to a) maintain an address map of at least one of the MLC and SLC non-volatile memory, the address map comprising a list of logical address ranges accessible by a computer system, the list of logical address ranges having a minimum quanta of addresses, wherein each entry in the list of logical address ranges maps to a similar range of physical addresses within either the at least one SLC non-volatile memory or within the at least one MLC non-volatile memory, b) determine if a range of addresses listed by an entry and mapped to a similar range of physical addresses within the at least one MLC non-volatile memory, at least one of the processor or the controller moves frequently written blocks of data to the SLC non-volatile memory from the MLC non-volatile memory as desired by the system, c) determine which of the blocks of the plurality of the blocks in the MLC and SLC non-volatile memory are accessed most frequently by maintaining a count of the number of times each one of the blocks is accessed and d) allocate those blocks that receive the most frequent writes by transferring the respective contents of those blocks to the at least one SLC non-volatile memory.