Delay circuitry based on pseudo-sram cells for controlling the sram sense amplifier timing

Abstract

Embodiments herein describe circuitry for mimicking SRAM cells. Instead of mimicking (or modeling) the entire SRAM cell, the mimic SRAM cells can mimic only the read path, which may include a pFET and two nFETs. In one embodiment, the mimic SRAM circuitry includes multiple selectable banks of mimic cells. During testing, the number of banks can be selected that best represent the worst case scenario—e.g., the PVT corner with the worst process variation. In addition to selecting the number of banks of mimic cells, the gate voltage of the transistors in the mimic cells can be adjusted.