Memory device and method of operating the same

Abstract

Provided is a memory device including a chip select (CS) buffer that is configured to output a first internal chip selection signal, a command clock (CK) buffer that is configured to output an internal clock signal, a command/address (CA) buffer that that is configured to output a first internal command/address signal, a CA buffer controller configured to control on/off of the CA buffer based on the first internal chip selection signal, synchronize the first internal chip selection signal and the first internal command/address signal to the internal clock signal, and delay the phase of a second internal chip selection signal synchronized to the internal clock signal, and a command decoder configured to decode any one of the second internal chip selection signal, a phase-delayed third internal chip selection signal, and/or a second internal command/address signal synchronized with the internal clock signal.