The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 08, 2026
Filed:
May. 14, 2024
Chongqing Boe Display Technology Co., Ltd., Chongqing, CN;
Boe Technology Group Co., Ltd., Beijing, CN;
Ming Hu, Beijing, CN;
Rui Wang, Beijing, CN;
Xiaoling He, Beijing, CN;
Xiangdan Dong, Beijing, CN;
Haigang Qing, Beijing, CN;
Gukhwan Song, Beijing, CN;
Yuanyou Qiu, Beijing, CN;
Runxin Zhang, Beijing, CN;
Zhiliang Jiang, Beijing, CN;
Yi Zhang, Beijing, CN;
Xueguang Hao, Beijing, CN;
Shouqiang Zhang, Beijing, CN;
Chao Zeng, Beijing, CN;
Ni Yang, Beijing, CN;
Yao Huang, Beijing, CN;
Hongtao Weng, Beijing, CN;
Chongqing BOE Display Technology Co., Ltd., Chongqing, CN;
BOE Technology Group Co., Ltd., Beijing, CN;
Abstract
An array substrate includes a substrate and pixel circuits disposed on the first substrate. A pixel circuit includes a first light-emitting control transistor and a second light-emitting control transistor. The array substrate further includes a first light-emitting control signal line and a second light-emitting control signal line. The first light-emitting control signal line is electrically connected to a gate of the first light-emitting control transistor. The second light-emitting control signal line is electrically connected to a gate of the second light-emitting control transistor. The array substrate further includes conductive layers. The first light-emitting control signal line and the second light-emitting control signal line are electrically insulated. The first light-emitting control signal line and the second light-emitting control signed line are located in different conductive layers. Orthographic projections on the substrate, of the first light-emitting control signal line and the second light-emitting control signal line do not overlap.