The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 08, 2026
Filed:
Mar. 20, 2024
Stmicroelectronics S.r.l., Agrate Brianza, IT;
Cesare Bimbi, Paterno', IT;
Salvatore Giuseppe Privitera, Paterno', IT;
Francesco Pulvirenti, Acireale, IT;
STMICROELECTRONICS S.r.l., Agrate Brianza, IT;
Abstract
The present disclosure is directed to a voltage regulation circuit receiving as input an input voltage, in particular a DC voltage supply, and outputting a regulated voltage. The voltage regulation circuit includes a voltage reference circuit configured to supply a reference voltage which is independent, in particular with respect to temperature variations. The voltage regulation circuit includes a first circuit branch and a second circuit branch in parallel coupled between the input voltage and ground. The first branch includes a current generator including a first depletion MOSFET transistor, which gate source voltage is a PTAT (Proportional To Absolute Temperature) voltage, coupled between the input voltage and the voltage reference circuit. The voltage reference circuit includes a first enhancement MOSFET transistor, which gate source voltage is a CTAT (Complementary To Absolute Temperature) voltage, coupled to the ground by its source through a source resistor, on which a reference voltage, sum of the PTAT voltage drop on the source resistor and of the gate source voltage of the enhancement MOSFET transistor being formed. The first enhancement MOSFET transistor is arranged on the first branch and coupled by the drain to the first depletion MOSFET transistor in a control node. The control node is coupled to the gate of the first enhancement MOSFET transistor. The first depletion MOSFET transistor injects a PTAT current in the first branch determining a PTAT voltage drop on the source resistor. The second branch includes an output stage coupled between the voltage to regulate and an output node on which the regulated voltage is taken. The output stage includes a second depletion MOSFET transistor on which output is taken at the output node. A resistive voltage divider is coupled to the output node, outputting on a respective divider output node a divided output regulated voltage which is inputted as the process variable of a negative feedback loop which is also coupled to the reference voltage. The output of the negative feedback loop controls the gate of the second MOSFET transistor.