The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 01, 2026

Filed:

Sep. 25, 2023
Applicant:

Powerchip Semiconductor Manufacturing Corporation, Hsinchu, TW;

Inventor:

Takeo Okamoto, Osaka, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10W 70/65 (2026.01); H10P 74/00 (2026.01); H10W 70/685 (2026.01); H10W 90/00 (2026.01); H10W 80/00 (2026.01); H10W 90/20 (2026.01); H10W 90/26 (2026.01);
U.S. Cl.
CPC ...
H10W 70/65 (2026.01); H10P 74/273 (2026.01); H10W 70/685 (2026.01); H10W 90/00 (2026.01); H10W 80/721 (2026.01); H10W 90/26 (2026.01); H10W 90/297 (2026.01); H10W 90/732 (2026.01); H10W 90/734 (2026.01); H10W 90/794 (2026.01);
Abstract

A memory tile with a probe pad arrangement and a stacked memory device are provided. The memory tile has a first and a second surfaces; a first probe pad set, having first probe pads and provided on the first surface; a second probe pad set, having second probe pads and provided on the second surface; first conductive connections, each of which is connected to a corresponding first probe pad; second conductive connections, each of which is connected to a corresponding first conductive connection; third conductive connections, each of which is connected to a corresponding second conductive connection; and fourth conductive connections, each of which is connected to a corresponding third conductive connection and to a corresponding second probe pad. The first and the second probe pad sets have the same arrangement pattern, and the same test signal pattern.


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