The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 01, 2026

Filed:

May. 11, 2023
Applicant:

Wistron Neweb Corporation, Hsinchu, TW;

Inventors:

Kuo-Hua Hsieh, Hsinchu, TW;

Chao-Chieh Chan, Hsinchu, TW;

Ming-Jhe Wu, Hsinchu, TW;

Chih-Yang Weng, Hsinchu, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10W 72/00 (2026.01); H10W 40/25 (2026.01); H10W 72/20 (2026.01); H10W 72/30 (2026.01); H10W 90/00 (2026.01); H10W 99/00 (2026.01);
U.S. Cl.
CPC ...
H10W 40/251 (2026.01); H10W 72/01223 (2026.01); H10W 72/01323 (2026.01); H10W 72/072 (2026.01); H10W 72/07202 (2026.01); H10W 72/07236 (2026.01); H10W 72/07237 (2026.01); H10W 72/07253 (2026.01); H10W 72/073 (2026.01); H10W 72/07302 (2026.01); H10W 72/07338 (2026.01); H10W 72/237 (2026.01); H10W 72/241 (2026.01); H10W 72/242 (2026.01); H10W 72/248 (2026.01); H10W 72/253 (2026.01); H10W 72/263 (2026.01); H10W 72/265 (2026.01); H10W 72/267 (2026.01); H10W 72/287 (2026.01); H10W 72/332 (2026.01); H10W 72/337 (2026.01); H10W 72/342 (2026.01); H10W 72/348 (2026.01); H10W 72/354 (2026.01); H10W 72/387 (2026.01); H10W 72/856 (2026.01); H10W 90/724 (2026.01); H10W 90/734 (2026.01); H10W 99/00 (2026.01);
Abstract

A package structure and a method for fabricating the same are provided. The package structure includes a substrate, a semiconductor package and an adhesive body. The substrate has a first board surface and a second board surface. The semiconductor package has an upper surface and a lower surface, is disposed on the first board surface and electrically connected to the substrate through pins, and has a first vertical projection on the first board surface. An adhesive groove is disposed on the first board surface and is located in at least one portion of the first vertical projection and a periphery of the first vertical projection. The adhesive body is disposed in the adhesive groove, and protrudes to contact the lower surface, so as to fix the semiconductor package. The adhesive groove does not overlap with the pins, and the adhesive body does not contact the pins.


Find Patent Forward Citations

Loading…