The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 01, 2026

Filed:

Nov. 15, 2022
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Myungsam Kang, Hwaseong-si, KR;

Yongjin Park, Yongin-si, KR;

Youngchan Ko, Seoul, KR;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H10W 40/22 (2026.01); H10P 72/70 (2026.01); H10W 42/20 (2026.01); H10W 70/02 (2026.01); H10W 70/05 (2026.01); H10W 70/60 (2026.01); H10W 70/65 (2026.01); H10W 70/685 (2026.01); H10W 74/01 (2026.01); H10W 74/10 (2026.01); H10W 90/00 (2026.01); H10W 70/09 (2026.01); H10W 70/652 (2026.01);
U.S. Cl.
CPC ...
H10W 40/228 (2026.01); H10P 72/74 (2026.01); H10W 40/22 (2026.01); H10W 42/20 (2026.01); H10W 70/02 (2026.01); H10W 70/05 (2026.01); H10W 70/093 (2026.01); H10W 70/611 (2026.01); H10W 70/614 (2026.01); H10W 70/65 (2026.01); H10W 70/685 (2026.01); H10W 74/016 (2026.01); H10W 74/019 (2026.01); H10W 74/117 (2026.01); H10W 90/00 (2026.01); H10P 72/7436 (2026.01); H10W 70/09 (2026.01); H10W 70/6528 (2026.01);
Abstract

A semiconductor package includes an interconnect structure having a first surface and a second surface opposing the first surface, and including a redistribution pattern and a vertical connection conductor, a first semiconductor chip disposed for a first inactive surface to oppose the first surface, a second semiconductor chip disposed on the first surface of the interconnect structure and disposed for the second inactive surface to oppose the first surface; a first encapsulant encapsulating the first and second semiconductor chips, a backside wiring layer disposed on the first encapsulant, a wiring structure connecting the redistribution pattern to the backside wiring layer, a heat dissipation member disposed on the second surface and connected to the vertical connection conductor.


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