The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 01, 2026

Filed:

Sep. 26, 2022
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Youngsang Cho, Seongnam-si, KR;

Heeseok Lee, Suwon-si, KR;

Yunhyeok Im, Hwaseong-si, KR;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H10W 40/22 (2026.01); H10W 40/25 (2026.01); H10W 70/65 (2026.01); H10W 70/68 (2026.01); H10W 70/685 (2026.01); H10W 74/10 (2026.01); H10W 90/00 (2026.01); H10W 70/60 (2026.01); H10W 74/00 (2026.01); H10W 90/20 (2026.01);
U.S. Cl.
CPC ...
H10W 40/22 (2026.01); H10W 40/258 (2026.01); H10W 70/65 (2026.01); H10W 70/68 (2026.01); H10W 70/685 (2026.01); H10W 74/121 (2026.01); H10W 74/124 (2026.01); H10W 90/00 (2026.01); H10W 90/401 (2026.01); H10W 90/701 (2026.01); H10W 70/60 (2026.01); H10W 74/00 (2026.01); H10W 90/288 (2026.01); H10W 90/722 (2026.01); H10W 90/724 (2026.01); H10W 90/732 (2026.01); H10W 90/734 (2026.01); H10W 90/754 (2026.01);
Abstract

A semiconductor package includes a first interconnection structure, a first semiconductor chip on the first interconnection structure, an encapsulant covering the first semiconductor chip, a second interconnection structure on the first semiconductor chip and the encapsulant, including a plurality of interconnection layers, and having an opening having a step portion, exposing a portion of an upper surface of at least one of the plurality of interconnection layers, and a heat dissipation pattern in the opening, passing through the encapsulant and in contact with at least a portion of an upper surface of the first semiconductor chip. The heat dissipation pattern includes a lower portion having a first width, and an upper portion on the lower portion and having a second width, and the upper portion of the heat dissipation pattern contacts the exposed portion of the upper surface of the at least one interconnection layer.


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