The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 01, 2026
Filed:
Dec. 22, 2020
Shanghai Ic R & D Center Co., Ltd., Shanghai, CN;
Ao Guo, Shanghai, CN;
SHANGHAI IC R & D CENTER CO., LTD., Shanghai, CN;
SHANGHAI INTEGRATED CIRCUIT EQUIPMENT & MATERIALS INDUSTRY INNOVATION CENTER CO., LTD, Shanghai, CN;
Abstract
The present invention is to provide a RRAM cell, comprising: two transistors which are coupled and resistive switching cells, and the number of the resistive switching cells is n; wherein electrodes of the resistive switching cells are connected in sequence to form a horizontal stack structure, and the same electrode is shared between any two adjacent resistive switching cells, the gates of the two transistors are used for applying different control signals respectively, the sources of the two transistors are connected together and used for applying a source signal jointly, drains of the two transistors are connected to one end of each of electrodes of different resistive switching cells which the number thereof is m in the resistive switching cells which the number thereof is n respectively, and the other ends of the electrodes of the resistive switching cells which the number thereof is n are used for applying different bit signals respectively. According to the present invention. Based on vertical channel transistors and resistance switching cells with a horizontal stacked structure, a 2TnR RRAM is formed in the present invention, which can simultaneously realize binary and multi value storage functions according to different operation timings, and cell area is controllable. It can be used to realize a high-density RRAM array and chip.
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile