The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 01, 2026

Filed:

Mar. 05, 2024
Applicant:

National Yang Ming Chiao Tung University, Hsinchu City, TW;

Inventors:

Bing-Yue Tsui, Hsinchu City, TW;

Li-Tien Hsueh, Taipei City, TW;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H10D 64/27 (2025.01); H10D 30/01 (2025.01); H10D 30/66 (2025.01); H10D 62/10 (2025.01);
U.S. Cl.
CPC ...
H10D 64/516 (2025.01); H10D 30/0297 (2025.01); H10D 30/668 (2025.01); H10D 62/127 (2025.01); H10D 64/513 (2025.01);
Abstract

A fabrication method for increasing bottom gate oxide thickness of a power transistor and trench gate structure formed by using the same are provided. A power transistor is provided, and a gate oxide layer is deposited along its trench. Two polysilicon sidewalls are formed and covering thereon. A barrier layer is provided on a side surface of each polysilicon sidewall. And wet etching process is used to remove the gate oxide layer underneath such that a vacancy is formed at the bottom of the trench. By oxidizing the polysilicon sidewalls, a thick oxide layer is formed and filling the vacancy. The disclosed barrier layer is used for avoiding the polysilicon sidewalls from lateral oxidation such that the process method is under better process control. By employing the present invention, it is advantageous of increasing bottom gate oxide thickness, reducing trench corner curvature as well as parasitic gate-drain capacitance.


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