The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 01, 2026
Filed:
Apr. 10, 2023
Applicant:
Century Technology (Shenzhen) Corporation Limited, Shenzhen, CN;
Inventors:
Chan-Kuan Huang, New Taipei, TW;
Tuan-Fei Gu, Shenzhen, CN;
Deng-Kai Chang, New Taipei, TW;
Tai-Hsing Lee, New Taipei, TW;
Assignee:
Century Technology (Shenzhen) Corporation Limited, Shenzhen, CN;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/786 (2006.01); G02F 1/1368 (2006.01); H10D 30/01 (2025.01); H10D 30/67 (2025.01); H10D 86/40 (2025.01); H10D 86/60 (2025.01);
U.S. Cl.
CPC ...
H10D 30/6757 (2025.01); G02F 1/1368 (2013.01); H10D 30/0316 (2025.01); H10D 30/0321 (2025.01); H10D 30/6732 (2025.01); H10D 30/6746 (2025.01); H10D 86/421 (2025.01); H10D 86/60 (2025.01);
Abstract
The present disclosure provides a TFT. The TFT includes a gate electrode, an insulating layer on the gate electrode, and an active layer on the insulating layer. The active layer includes an annealed layer and an a-Si layer. The annealed layer is between the a-Si layer and the insulating layer. The annealed layer is made of amorphous silicon material by excimer laser annealing. The present disclosure further provides a TFT array substrate and a method of manufacturing a TFT.