The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 01, 2026

Filed:

Feb. 22, 2023
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Beomjin Park, Suwon-si, KR;

Myung Gil Kang, Suwon-si, KR;

Dongwon Kim, Suwon-si, KR;

Younggwon Kim, Suwon-si, KR;

Sungkeun Lim, Suwon-si, KR;

Soojin Jeong, Suwon-si, KR;

Yuyeong Jo, Suwon-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10D 30/43 (2025.01); H10D 30/67 (2025.01); H10D 62/10 (2025.01); H10D 64/23 (2025.01);
U.S. Cl.
CPC ...
H10D 30/43 (2025.01); H10D 30/6735 (2025.01); H10D 62/121 (2025.01); H10D 64/258 (2025.01);
Abstract

A semiconductor device includes: a substrate that includes an active pattern; a channel pattern disposed on the active pattern, wherein the channel pattern includes a plurality of semiconductor patterns that are stacked on each other and spaced apart from each other; a source/drain pattern connected to the plurality of semiconductor patterns; a gate electrode disposed on the plurality of semiconductor patterns, the gate electrode extending in a first direction; a gate dielectric layer disposed between the plurality of semiconductor patterns and the gate electrode; and a lower dielectric pattern disposed between the active pattern and the gate dielectric layer, wherein the gate dielectric layer includes an interface layer and a high-k dielectric layer, wherein the interface layer covers the semiconductor patterns, wherein the high-k dielectric layer is disposed on the interface layer, and wherein a thickness of the lower dielectric pattern is greater than a thickness of the interface layer.


Find Patent Forward Citations

Loading…