The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 01, 2026
Filed:
Mar. 22, 2023
Samsung Electronics Co., Ltd., Suwon-si, KR;
Joonyoung Kwon, Suwon-si, KR;
Jiyoung Kim, Suwon-si, KR;
Woosung Yang, Suwon-si, KR;
Sukkang Sung, Suwon-si, KR;
Samsung Electronics Co., Ltd., Suwon-si, KR;
Abstract
A three-dimensional semiconductor memory device may include a first substrate, a peripheral circuit structure on the first substrate, the peripheral circuit structure including first bonding pads in an upper portion of the peripheral circuit structure, and a cell array structure on the peripheral circuit structure. The cell array structure may include a second substrate, a stack interposed between the peripheral circuit structure and the second substrate, a first insulating layer enclosing the stack, a dummy plug penetrating the first insulating layer, a second insulating layer on the dummy plug, and second bonding pads interposed between the stack and the peripheral circuit structure and connected to the dummy plug. The first bonding pads may contact the second bonding pads, and the dummy plug may be electrically connected to the first bonding pads and the second bonding pads. A top surface of the dummy plug may contact the second insulating layer.