The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 01, 2026

Filed:

May. 27, 2023
Applicant:

Icometrue Company Ltd., Zhubei, TW;

Inventors:

Mou-Shiung Lin, Hsinchu, TW;

Jin-Yuan Lee, Hsinchu, TW;

Assignee:

iCometrue Company Ltd., Hsinchu County, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 19/1776 (2020.01); G11C 11/16 (2006.01); G11C 11/412 (2006.01); G11C 11/419 (2006.01); G11C 13/00 (2006.01); G11C 14/00 (2006.01); H03K 19/0948 (2006.01); H03K 19/173 (2006.01); H03K 19/17728 (2020.01); H03K 19/20 (2006.01); H10B 10/00 (2023.01); H10B 61/00 (2023.01); H10B 63/00 (2023.01); H10N 70/00 (2023.01); H10W 70/60 (2026.01); H10W 70/65 (2026.01); H10W 90/00 (2026.01); H03K 19/21 (2006.01); H10W 72/00 (2026.01); H10W 72/20 (2026.01); H10W 74/15 (2026.01);
U.S. Cl.
CPC ...
H03K 19/1776 (2013.01); G11C 11/1673 (2013.01); G11C 11/412 (2013.01); G11C 11/419 (2013.01); G11C 13/0007 (2013.01); G11C 13/0038 (2013.01); G11C 13/004 (2013.01); G11C 14/0081 (2013.01); G11C 14/009 (2013.01); H03K 19/0948 (2013.01); H03K 19/1737 (2013.01); H03K 19/17728 (2013.01); H03K 19/20 (2013.01); H10B 10/00 (2023.02); H10B 10/15 (2023.02); H10B 61/00 (2023.02); H10B 61/10 (2023.02); H10B 63/00 (2023.02); H10B 63/20 (2023.02); H10B 63/30 (2023.02); H10B 63/80 (2023.02); H10N 70/826 (2023.02); H10N 70/841 (2023.02); H10N 70/8833 (2023.02); H10W 70/611 (2026.01); H10W 70/65 (2026.01); H10W 90/00 (2026.01); H10W 90/701 (2026.01); G11C 2213/15 (2013.01); H03K 19/21 (2013.01); H10W 72/0198 (2026.01); H10W 72/072 (2026.01); H10W 72/07207 (2026.01); H10W 72/073 (2026.01); H10W 72/222 (2026.01); H10W 72/241 (2026.01); H10W 72/242 (2026.01); H10W 72/244 (2026.01); H10W 72/252 (2026.01); H10W 74/15 (2026.01); H10W 90/724 (2026.01);
Abstract

A multi-chip package includes a field-programmable-gate-array (FPGA) integrated-circuit (IC) chip configured to perform a logic function based on a truth table, wherein the field-programmable-gate-array (FPGA) integrated-circuit (IC) chip comprises multiple non-volatile memory cells therein configured to store multiple resulting values of the truth table, and a programmable logic block therein configured to select, in accordance with one of the combinations of its inputs, one from the resulting values into its output; and a memory chip coupling to the field-programmable-gate-array (FPGA) integrated-circuit (IC) chip, wherein a data bit width between the field-programmable-gate-array (FPGA) integrated-circuit (IC) chip and the memory chip is greater than or equal to 64.


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