The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 01, 2026
Filed:
Nov. 27, 2023
Chengdu Pbm Technology Ltd, Chengdu, CN;
Jack Zezhong Peng, Chengdu, CN;
Ke Wang, Chengdu, CN;
Chengdu PBM Technology Ltd, Chengdu, CN;
Abstract
Provided are a high-voltage blocking device (HVBD), a three-dimensional memory, and a preparation method thereof, relating to the technical field of three-dimensional memory manufacturing. The HVBD layer is provided with a plurality of vertical MOS through-holes; HVBDs are embedded in the HVBD layer through the corresponding vertical MOS through-holes; the HVBD layer includes a decoder array connection layer, a gate control layer, and a bit line connection layer that are sequentially arranged from bottom to top; the decoder array connection layer, the gate control layer, and the bit line connection layer are each provided with a plurality of MOS through-holes. This application, by embedding the HVBDs between a bit line decoder array and a three-dimensional stacked memory array, can reduce a planar area occupied by the three-dimensional memory while preventing electrical breakdown of a gate insulating layer of a bit line selection transistor.