The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 01, 2026

Filed:

Nov. 09, 2023
Applicant:

SK Hynix Inc., Icheon-si, KR;

Inventors:

In Gon Yang, Icheon-si, KR;

Jae Hyeon Shin, Icheon-si, KR;

Assignee:

SK hynix Inc., Icheon-si, KR;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C 16/34 (2006.01); G11C 16/24 (2006.01);
U.S. Cl.
CPC ...
G11C 16/3459 (2013.01); G11C 16/24 (2013.01); G11C 16/3404 (2013.01);
Abstract

A page buffer of a semiconductor memory device includes a bit line connection transistor, an internal operation circuit, and a plurality of latch circuits. During a program operation of selected memory cells, a power voltage is applied to the bit line connection transistor to set a voltage of a bit line connected to memory cells having a threshold voltage greater than a main verify voltage as a program inhibit voltage. In addition, a second program allowable voltage less than the program inhibit voltage is applied to the bit line connection transistor. In addition, a first program allowable voltage less than the second program allowable voltage is applied to the gate of the bit line connection transistor.


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