The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 01, 2026

Filed:

Jul. 11, 2022
Applicant:

Lx Semicon Co., Ltd., Daejeon, KR;

Inventors:

Jin Su Byeon, Daejeon, KR;

Cheol Ho Lee, Daejeon, KR;

Yoon Soo Shin, Daejeon, KR;

Assignee:

LX SEMICON CO., LTD, Daejeon, KR;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G09G 3/20 (2006.01);
U.S. Cl.
CPC ...
G09G 3/20 (2013.01); G09G 2300/0426 (2013.01); G09G 2310/0289 (2013.01); G09G 2310/0297 (2013.01); G09G 2310/08 (2013.01); G09G 2330/021 (2013.01); G09G 2330/028 (2013.01); G09G 2330/06 (2013.01);
Abstract

The present disclosure relates to a power management integrated circuit and a gate clock modulation circuit, the power management integrated circuit including a delay circuit configured to delay, by a preset time, and output an on clock signal for setting an output start time point of a gate driving circuit and an off clock signal for setting an initialization time point of the gate driving circuit; a multiplexer configured to select and output one among delayed signals transferred through signal lines which are connected to the delay circuit; and a gate clock generation circuit configured to generate a gate clock signal by using the on clock signal and the off clock signal outputted from the multiplexer.


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