Designing approximate adder circuits using reinforcement learning

Abstract

Methods, systems, and apparatus, including computer programs encoded on a computer storage medium for designing approximate adder circuits. In one aspect, a method includes: initializing a parallel prefix graph representing a parallel prefix circuit; and for each step in a sequence of steps: obtaining a current state of the parallel prefix graph; processing the current state using a neural network to generate a policy for adding or deleting nodes in the parallel prefix graph; adding or deleting a node in the parallel prefix graph while subject to one or more constraints; synthesizing the parallel prefix circuit having logic circuits corresponding to nodes in the parallel prefix graph; generating a respective value for each of multiple circuit-based metrics; determining a reward based on the values of the circuit-based metrics; and training the network parameters of the neural network on the reward using a reinforcement learning algorithm.