The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 01, 2026
Filed:
Mar. 04, 2024
Xilinx, Inc., San Jose, CA (US);
Paul S. Levy, Albuquerque, NM (US);
XILINX, INC., San Jose, CA (US);
Abstract
Embodiments herein describe CRAM validation using an external device (ED). The ED selects unused addresses of CRAM as challenge registers (CRs), determines challenge bits for the CRs, and provides the selected addresses and the challenge bits to challenge circuitry of the IC device. The challenge circuitry initiates storage of the challenge bits at the selected CRAM addresses and invokes scan circuitry to scan the CRAM. The scan circuitry retrieves contents of CRAM addresses used to store configuration bits and contents of the selected CRAM addresses, and provides the contents or a code determined from the contents to the challenge circuitry (i.e., bypassing validation circuitry of scan logic). The challenge circuitry forwards the contents or the code to the ED as a challenge response, and the ED validates the CRAM based on the challenge response and a golden copy of the configuration bits.