The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 01, 2026

Filed:

Dec. 06, 2024
Applicant:

Electronics and Telecommunications Research Institute, Daejeon, KR;

Inventors:

Eun-Ji Pak, Daejeon, KR;

Kwang-Won Koh, Daejeon, KR;

Chang-Dae Kim, Daejeon, KR;

Tae-Hoon Kim, Daejeon, KR;

Yeon-Jeong Jeong, Daejeon, KR;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06N 3/065 (2023.01); G06F 3/06 (2006.01); G06F 12/02 (2006.01); G06F 17/16 (2006.01); G06F 12/06 (2006.01);
U.S. Cl.
CPC ...
G06F 3/0616 (2013.01); G06F 3/0659 (2013.01); G06F 3/0673 (2013.01); G06N 3/065 (2023.01); G06F 3/0688 (2013.01); G06F 12/0207 (2013.01); G06F 12/06 (2013.01); G06F 17/16 (2013.01);
Abstract

Disclosed herein are an apparatus and method for managing memory cell endurance of an analog computing system. The apparatus for managing memory cell endurance of an analog computing system includes memory configured to store at least one program and a processor configured to execute the program, wherein the program is configured to determine analog processing elements in which matrix data is to be arranged and write matrix data to the determined analog processing elements, and as an update for matrix data stored in the analog processing elements occurs, write updated matrix data to memory cells selected based on a number of write operations on internal memory cells of each of the analog processing elements.


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