The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 25, 2026

Filed:

Dec. 29, 2022
Applicant:

Analog Devices International Unlimited Company, Limerick, IE;

Inventors:

Fatih Kocer, Boxboro, MA (US);

Christoph Maximilian Steinbrecher, Pennington, NJ (US);

Sacid Oruc, Yenimahalle, TR;

Ekrem Oran, Hollis, NH (US);

Santosh Anil Kudtarkar, Ayer, MA (US);

Arun Raj, Woburn, MA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H10W 42/00 (2026.01); H10W 70/60 (2026.01); H10W 70/65 (2026.01); H10W 70/685 (2026.01); H10W 76/17 (2026.01); H10W 90/00 (2026.01);
U.S. Cl.
CPC ...
H10W 42/00 (2026.01); H10W 70/611 (2026.01); H10W 70/65 (2026.01); H10W 70/685 (2026.01); H10W 76/17 (2026.01); H10W 90/724 (2026.01);
Abstract

An electronic device package may include an integrated circuit die mounted on a package substrate, the package substrate may include a dielectric medium, the integrated circuit die may include respective electrical interconnects located between the integrated circuit die and the dielectric medium. The electronic device package may also include a first transmission line which may be embedded within the dielectric medium, the first transmission line may be fed by the integrated circuit die from at least one of the respective electrical interconnects and through a corresponding first via structure in the dielectric medium. The integrated circuit die may one or more of include or be attached to a conductive plane that extends to overlap with a location of the first via structure in the dielectric medium. The conductive plane may be connected to a first return structure of the first transmission line by one or more conductive pillars.


Find Patent Forward Citations

Kocer, Fatih. (2026). Integrated curcuit to dielectric substrate transition (U.S. Patent No. 12721171). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12721171

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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