The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 25, 2026

Filed:

May. 16, 2022
Applicant:

Applied Materials, Inc., Santa Clara, CA (US);

Inventors:

Tyler Sherwood, Fonda, NY (US);

Raghav Sreenivasan, Fremont, CA (US);

Assignee:

Applied Materials, Inc., Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10H 20/01 (2025.01); H10H 20/825 (2025.01); H10W 42/00 (2026.01); H10W 90/00 (2026.01);
U.S. Cl.
CPC ...
H10H 20/01335 (2025.01); H10W 42/121 (2026.01); H10W 90/00 (2026.01); H10H 20/825 (2025.01);
Abstract

A microLED-quality layer of gallium nitride (GaN) may be formed above a silicon substrate for microLED devices to be formed. Typically, mismatches between the crystal lattice of the GaN and the silicon substrate cause internal stresses that bow the wafer. To relieve these stresses, a pattern of trenches may be etched into the GaN layer between the die or device footprints. These trenches may be etched through the GaN layer, down to the depth of the silicon substrate, or even down into the silicon substrate. Instead of one singular, large wafer with internal stresses, the wafer may thus be divided into multiple small sections with minimal internal stresses. A dielectric gap fill may be applied to fill the trenches, and the resulting wafer may be planarized to expose the surface of the GaN after the gap fill.


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