The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 25, 2026

Filed:

Mar. 18, 2022
Applicant:

Cactus Materials, Inc., Tempe, AZ (US);

Inventors:

Rafiqul Islam, Gilbert, AZ (US);

Sager Ayyoub, Glendale, AZ (US);

Assignee:

Cactus Materials, Inc., Tempe, AZ (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H10F 77/14 (2025.01); H10F 30/225 (2025.01); H10P 10/00 (2026.01); H10P 90/00 (2026.01);
U.S. Cl.
CPC ...
H10F 77/14 (2025.01); H10F 30/225 (2025.01); H10P 10/128 (2026.01); H10P 10/14 (2026.01); H10P 90/1914 (2026.01);
Abstract

A method of manufacturing a semiconductor substrate having a deep junction, forming at least one p+ region (n+ region) on a front side of a p-type (n-type) high-resistance wafer; and forming at least one n+ region (p+ region) on a front side of a n-type (p-type) high-resistance wafer. The method further includes aligning the at least one p+ region (n+ region) on a front side of a p-type (n-type) high-resistance wafer with the at least one n+ region (p+ region) on a front side of a n-type (p-type) high-resistance wafer; and bonding the front sides of the high-resistance wafers to form a wafer assembly having at least one deep p-n junction at a depth of at least 1 micron from the backside of the n-type (p-type) high-resistance wafer.


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