The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 25, 2026

Filed:

Feb. 02, 2023
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventor:

Kyungdon Mun, Suwon-si, KR;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H10B 80/00 (2026.01); H10W 70/60 (2026.01); H10W 72/00 (2026.01); H10W 72/20 (2026.01); H10W 72/30 (2026.01); H10W 72/90 (2026.01); H10W 74/15 (2026.01); H10W 90/00 (2026.01);
U.S. Cl.
CPC ...
H10B 80/00 (2023.02); H10W 70/611 (2026.01); H10W 90/401 (2026.01); H10W 72/07254 (2026.01); H10W 72/07354 (2026.01); H10W 72/247 (2026.01); H10W 72/347 (2026.01); H10W 72/877 (2026.01); H10W 72/942 (2026.01); H10W 72/944 (2026.01); H10W 74/15 (2026.01); H10W 90/724 (2026.01); H10W 90/734 (2026.01); H10W 90/792 (2026.01); H10W 90/794 (2026.01);
Abstract

A semiconductor package may include a base wiring structure, a first bridge chip and a cache memory chip on the base wiring structure and spaced apart from each other in a horizontal direction, and logic semiconductor chips adjacent to each other on the first bridge chip and the cache memory chip. Logic semiconductor chips each may include a cache memory. The first bridge chip may overlap at least two of the logic semiconductor chips in a vertical direction and the first bridge chip may include first bridge wirings electrically connecting at least two of the logic semiconductor chips. The cache memory chip may overlap the cache memory of at least one of the logic semiconductor chips in the vertical direction and the cache memory chip may be electrically connected to the cache memory of at least one of the logic semiconductor chips.


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Mun, Kyungdon. (2026). Semiconductor package (U.S. Patent No. 12720769). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12720769

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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