The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 25, 2026

Filed:

Aug. 31, 2023
Applicant:

Texas Instruments Incorporated, Dallas, TX (US);

Inventors:

Win Naing Maung, Plano, TX (US);

Roy Wojciechowski, Round Rock, TX (US);

James Skidmore, Frisco, TX (US);

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H04L 12/40 (2006.01);
U.S. Cl.
CPC ...
H04L 12/40058 (2013.01); H04L 12/40013 (2013.01); H04L 12/40071 (2013.01); H04L 12/40117 (2013.01);
Abstract

A serial bus control circuit includes a link layer control circuit. The link layer control circuit is configured to control isochronous data transfer over a serial bus. The link layer control circuit includes an isochronous cycle timer configured to provide a cycle frame that is less than 125 microseconds in duration. The link layer control circuit can be configured to set the isochronous cycle timer to provide a cycle frame duration that produces an isochronous transfer latency of no more than 50 microseconds.


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Maung, Win. (2026). Low latency serial bus (U.S. Patent No. 12719715). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12719715

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