The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 25, 2026

Filed:

Mar. 20, 2024
Applicant:

Qualcomm Incorporated, San Diego, CA (US);

Inventors:

Jize Jiang, Singapore, SG;

Hua Guan, San Diego, CA (US);

Assignee:

Qualcomm Incorporated, San Diego, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G05F 1/575 (2006.01); G05F 3/26 (2006.01); H03F 3/45 (2006.01);
U.S. Cl.
CPC ...
H03F 3/45748 (2013.01); G05F 1/575 (2013.01); G05F 3/262 (2013.01); H03F 3/45273 (2013.01);
Abstract

Techniques and apparatus for supplying power with offset voltage generation are provided. One example power supply circuit generally includes a first transistor including a source coupled to an input voltage (Vin) node and a drain coupled to an output voltage (Vout) node, a second transistor including a drain coupled to a gate of the first transistor, a third transistor including a drain coupled to the drain of the second transistor and to the gate of the first transistor, where a source of the third transistor is coupled to a reference potential node of the power supply circuit, an amplifier including a first input coupled to a reference voltage (Vref) node and an output coupled to a gate of the third transistor, and a voltage offset circuit coupled between the gate of the first transistor and a gate of the second transistor.


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