The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 25, 2026

Filed:

Jul. 25, 2024
Applicant:

Semiconductor Energy Laboratory Co., Ltd., Kanagawa-ken, JP;

Inventor:

Atsushi Umezaki, Isehara, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 19/00 (2006.01); G09G 3/20 (2006.01); G09G 3/36 (2006.01); G11C 19/28 (2006.01); H10D 30/67 (2025.01); H10D 84/83 (2025.01); H10D 86/40 (2025.01); H10D 86/60 (2025.01); H10H 29/14 (2025.01); H10K 59/12 (2023.01);
U.S. Cl.
CPC ...
G11C 19/28 (2013.01); G09G 3/20 (2013.01); G09G 3/3674 (2013.01); G11C 19/287 (2013.01); H10D 30/6755 (2025.01); H10D 84/83 (2025.01); H10D 86/423 (2025.01); H10D 86/441 (2025.01); H10D 86/60 (2025.01); H10H 29/142 (2025.01); G09G 3/2092 (2013.01); G09G 3/3677 (2013.01); G09G 2310/0267 (2013.01); G09G 2310/0286 (2013.01); H10K 59/12 (2023.02);
Abstract

A semiconductor device which shifts a low-level signal is provided. In an example, a first transistor including a first terminal electrically connected to a first wiring and a second terminal electrically connected to a second wiring, a second transistor including a first terminal electrically connected to a third wiring and a second terminal electrically connected to the second wiring, a third transistor including a first terminal electrically connected to a fourth wiring and a second terminal electrically connected to a gate of the second transistor, a fourth transistor including a first terminal electrically connected to a fifth wiring, a second terminal electrically connected to a gate of the third transistor, and a gate electrically connected to a sixth wiring, and a first switch including a first terminal electrically connected to the third wiring and a second terminal electrically connected to a gate of the first transistor are included.


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