The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 25, 2026
Filed:
May. 23, 2024
Kioxia Corporation, Tokyo, JP;
Junya Matsuno, Yokohama Kanagawa, JP;
Kenro Kubota, Fujisawa Kanagawa, JP;
Masato Dome, Yokohama Kanagawa, JP;
Kensuke Yamamoto, Yokohama Kanagawa, JP;
Kei Shiraishi, Kawasaki Kanagawa, JP;
Kazuhiko Satou, Yokohama Kanagawa, JP;
Ryo Fukuda, Yokohama Kanagawa, JP;
Masaru Koyanagi, Tokyo, JP;
Kioxia Corporation, Tokyo, JP;
Abstract
A semiconductor memory device includes a memory cell array having a memory cell; a data signal terminal configured to receive data to be written into the memory cell from an exterior of the semiconductor memory device and to output data read from the memory cell to the exterior of the semiconductor memory, and a timing signal terminal configured to receive a timing control signal. An interface circuit includes a first comparator having a first input terminal connected to the data signal terminal, a second input terminal connected to a reference voltage, and an output terminal. A plurality of first inverters are connected in series, an input terminal of a first stage one of the first inverters being connected to the output terminal first of the first comparator. A first switch circuit has a first terminal connected to an output terminal of a final stage one of the first inverters and a second terminal; a second inverter having an input terminal connected to the second terminal of the first switch and an output terminal connected to the second terminal of the first switch; and a first latch circuit connected to the second terminal of the first switch.